Electronic adding devices



March 12, 1957 F. c. WILLIAMS ETAL 2,784,907

ELECTRONIC ADDING DEVICES 4 Sheets-Sheet l Filed 'April 30, 1952 S55 Skuwwmw N .Mr

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March 12, 1957 F. c. WILLIAMS ETAL 2,784,907

ELECTRONIC ADDING DEVICES Filed April so, 1952 4 sheets-sheet 2 March12, 1957 F. c. WILLIAMS ET AL 2,784,907

ELECTRONIC ADDING DEVICES Filed April 30, 1952 4 Sheets-Sheet 3 im mlm Ammm" EMU .4 Arq( Filed April' so. 1952 F. C. WILLIAMS ETAL ELECTRONICADDING DEVICES 4 Sheets-Sheet 4 61 Z2 5 4 Z5 (2) (2') (22) (23) (24)(20| +5V (w) il" b i o', ai a e l.: L@ Il 2 5 g I) (C) M /L/ Mu/.fr/-l/vPuT ADD/NG DEV/cf GATE CIRCUITS ELECTRONIC ADDNG DEVICES FredericGalland Williams, Timperley, and rEoin Kilburn,

Davyhulme, Manchester, England, and Dennis Lawrence Harold Gibbings,Croydon, New South Wales, Australia, assignors to National ResearchDevelopment Corporation, London, England, a corporation oi Great BritainApplication April 30, i952, Serial No. 285,148

Claims priority, application Great Britain May 8, 195i Z2. Claims. (Cl.Z3561) This invention relates to improvements in electronic digitalcomputing devices and is more particuiarly concerned with an improvedarrangement for effecting addition of binary numbers when represented byelectric pulse signal trains.

In copending patent applica-tion Serial No. 105,352, now Patent No.2,749,034, there is described an improved circuit arrangement for addingtogether two binary numbers, each represented simultaneously in dynamicform by electric pulse signal trains, and obtaining therefrom a furtherelectric pulse signal train which represents, again in dynamic form, thesum of the initial binary numbers.

The present invention has for its 'object the provision of anarrangement which is capable of accepting simultaneously on separateinput leads a considerable number of separate input pulse trainsV eachrepresentative in dynamic form of separate binary numbers and providingon a single output lead a further pulse signal train representative ofthe sum of all of the input numbers.

ln an arrangement according to the invention there is first derived foreach digit position of the simultaneously applied input signals, asingle signal pulse whose amplitude lever represents the analogue sum ofthe total number of input pulses simultaneously occurring in the groupof input leads, said derived sum-representing signal being then appliedto each of a plurality #of amplitude-discriminator circuits havingdifferent discrimination levels and providing a characteristic outputsignal only When such level is exceeded, such discriminator outputsignals being then used each to cause, in these amplitude-discriminatorcircuits having lower discrimination levels, the subtraction from saidderived sum-representing pulse of an amount which is representative ofthe discrimination level of the amplitude-discriminator circuit fromwhich lthe particular output signal was derived and also each to causethe eleotive reapplication to the means by which said firstsum-representing signal was derived of an input equivalent to the samenumber represented by then used each to cause, in thoseamplitude-discriminanator circuit having the lowest discrimination levelprovding a pulse signal train which is representative of the binarynumber constituting the sum of said input numbers.

One particular arrangement according to the invention comprises meanshaving a plurality of separate input terminals for deriving a signalpulse whose amplitude is representative of the sum of the number of ldigit-representing signals simultaneously occurring at any instant atsaid input terminals, a plurality of amplitude discriminator circuitseach of which is arranged to provide a characteristic output signalwhenever the resultant amplitude on one or more input pulse signalssimultaneously applied thereto exceeds a predetermined level, therespective predetermined discrimination levels for said circuits beingof diiierent and progressively increased amplitude values related to theascending significance values of the binary scale of numbers, means forapplying fnited States Patent i 2,784,907 Patented Mar. l2, i957 ICCsaid sum-representing pulse as one input to each of said amplitudediscriminator circuits, means for utilising the characteristic outputsignal from each of said amplitude discriminator circuits except that ofthe lowest discrimination level to cause simultaneous application to allof the amplitude discrimination circuits of lower discrimination levelsof an input signal which is eective to subtract from the amplitude ofthe applied sum-representing pulse simultaneously fed to such circuitsby an amount which is related to its own signiiicance in the binaryscale of numbers, further means for utilising the characteristic outputsignal from each one of said amplitude discriminator circuits exceptthat of the lowest discrimination level to cause reapplication to saidsum-pulse deriving means of an input representative of the binary numbervalue of that particular amplitude discriminator circuit from which itwas derived and output terminal means in said amplitude discriminatorcircuit of lowest discrimination level for delivering an elec-tricsignal pulse train representing the binary sum of the numbersrepresented by the separate pulse trains applied to said separate inputterminals.

In order that the various aspects of the invention may be more readilyunderstood certain constructional embodiments thereof will now bedescribed with reference to the accompanying drawings in which:

Fig. 1 is a block schematic diagram of an arrangement according to theinvention for accepting up to twenty-seven separate and simultaneouslyoccurring input pulse signal trains each representative of binarynumbers which are required to be added.

Fig. 2 is a circuit diagram 'of one form ot' analogue sum derivingdevice for the arrangement of Fig. 1.

Fig. 3 is a circuit diagram of one of the amplitude discriminatordevices of the arrangement of Fig. l while Fig. 4 is a similar circuitdiagram of another of the amplitude discriminator devices of the samearrangement.

Fig. 5 is a circuit diagram of one form of the amplitude discriminatordevice of the arrangement of Fig. l which provides the sum-representingoutput signal.

Fig. 6 is a series of explanatory Waveform diagrams.

Fig. 7 is a fragmentary view of part of Fig. l showing a modiedarrangement.

Fig. 8 is a block schematic diagram of an arrangement for multiplyingbinary numbers embodying the addmg arrangement of the present invention.

The broad outline of the invention and its manner of operation will rstbe given with reference to Fig. l. Referrmg to this ligure, the variousinput electric pulse signal trains, each representing one 'of thedifferent binary numbers which are to be added and wherein the variousdlgit-representing signals of similar binary power significance occursimultaneously', are applied separately on the various input leads lLl,lL2 lL2'7 to an analogue sunderiving circuit ASDC. This circuit has fouradditlonal input connections IL28 lLSl whose purpose Will be describedlater. The circuit serves to provlde on its output lead lil, an outputpulse Whose amplitude 1s proportional to the total number of binary lrepresenting digit signals which are present simultaneously upon thevarious input leads lLl Ill regardless of what leads are active at anyone time. This output pulse, which may thus have an amplitude which 1s`variable in unit steps between zero and thirty-one times apredetermined unit amplitude, is applied as a controlling mput signal toeach of the input terminals il, l2, 13, l-i and 1S respectively of fiveseparate amplitude-discriminator circuits ADCl, ADCZ, ADCS, ADCl andADC.

Each of the amplitude discriminator circuits except that of ADCS isprovided with one or more additional input terminals and Whose functionis to allow the controlled application of potentials which operatesubtractively upon the output pulse from the circuit ASDC so as todecrease its effective amplitude by a predetermined number of said unitamplitude steps. Eachy of the amplitude discriminator circuits ABC1 ABCSoperates to provide an output pulse when, and only when, tl'ie effectiveamplitude of the output pulse from circuit ASDC, after any subtractionsthat may be made, has a value which exceeds the particular predetermineddiscrimination level of the circuit.

The amplitude discriminator circuit ADCI has a discrimination levelequal to one-half that of the aforesaid unit amplitude for the outputpulse from the analogue sum deriving circuit ASDC while the amplitudediscriminator circuit ABC2 has a discrimination level of one and a halfof such amplitude units, the amplitude discriminator circuit ABCS adiscriminationlevel of three and a half. amplitude units, the amplitudediscriminator circuit ABC4 a discrimination level of seven and a halfamplitude units and the amplitude discriminator circuit ABCS adiscrimination level of fifteen 1and a half amplitude units.

The output lead 16 from the amplitude discriminator circuit ABClconstitutes the final output connection of the arrangement and deliversa pulse signal train representing, in dynamic serial form, the binarysum number S of the various input binary numbers applied as electricpulse signal trains to the input leads lLl lL27.

The output `from lthe amplitude discriminator circuit ABC2 is appliedover lead 17 as the controlling medium for a single control gate circuitGC1 through which a potential causing the effective subtraction of twoof the aforesaid amplitude units from the value of the input pulsearriving `at terminal 11 from the analogue sum deriving circuit ASDC,may be `applied over lead 21 to the amplitude discrminator circuit ADCI.VThe same output from the amplitude discriminator'circuit ABC2 on leadA17 is lalso fed to a delay circuit BClwhich serves to impose upon anysignal applied thereto a time delay equal to one digit-interval time ofthe input pulse signal trains supplied to vthe input leadslLl IL27. Thedelayed signal output from this delay circuit DCI is then fed back tothe analogue sum deriving circuit ASDC as an additional input on theinput lead 11.28. r[he form of the signal supplied from the delay deviceBCI is such that it constitutes the equivalent of a binary "lrepresenting signal occurring one digit interval later than that inwhich the initiating output appeared from the circuit ABC2.

The output from the amplituderdiscriminator circuit ABCS is similarlyapplied over lead 18 to control two .gate circuits GCZ, GCS which governrespectively the application to cach of the amplitude discriminatorcircuits ABCE and ABC2, by way of leads 22, 23, of a potential whichcauses the subtraction of four of the aforesaid amplitude units from thevalue of the input pulsearriving at terminals l1 and 12 of thosecircuits, The same output from the amplitude discriminator circuit ABC3on lead 18 is also applied through a second delay circuit DCZ, whichimposes a time delay equal to two digit-interval time periods 'of theinput pulse signal trains used, to the further input lead IL29 of theanalogue sum deriving circuit ASBC. This signal forms the equivalent ofa l representing signal occurring two digit intervals later than that inwhich the initiating signal appeared at the output from the circuitADC3.

In similar manner the output on lead 19 from amplitude discriminatorcircuit ABC4 is used to control three separate gate circuits GC4, GCSand GCG which govern respectively the application, through leads 2.4, 2Sand 26, of a potential which causes the effective subtraction of eightof the aforesaid amplitude units from the value of the input pulsearriving at terminals 11, 12 and 13 of the amplitude discriminatorcircuits ADCI, ABC2 and ABC3. The same` output on lead 19 is alsoapplied through a delay circuit DC3, which imposes a time delay equal tothree digit-interval time periods of the input signal pulse trains, tothe additional input lead IL30 of the 4 analogue sum deriving circuitASDC. This input signal torms the equivalent of a "1 representing signaloccurring three digit intervals later than that in which the initiatingsignal appeared at the output from circuit ABC4.

The output on lead 20 from amplitude discriminator circuit ABCS islikewise used to control four additional gate circuits GC7, GCS, GC9 andGCM which govern respectively the application, by way of leads 27, 28,29 and 3?, of a potential which cau-ses the eiective subtraction ofsixteen of the aforesaid amplitude units from the value of the inputpulse arriving at the terminals 11, 12, 13 and le? of the amplitudediscriminator circuits ADCI, ABC2, ABCB and ABCd of lower discriminationlevels. The output on lead Ztl is also applied by way of further delaycircuit DCd, which imposes a delay equal to four of the digit intervaltime periods of the input pulse signal trains, to the fourth of theadditional input leads lLSl of the analogue sum deriving circuit ASDC,This input signal forms the equivalent of a "1 representing signaloccurringr four digit intervals later' than that in which the initiatingsignal appeared at the output from circuit ABCS.

Operation ln describing the operation of the above arrangement therewill be taken `as an example the simultaneous occurrence, on fourteen ofthe twenty-seven input leads IL lL2'7, of the binary equivalent of thedecimal number l, that is a single "l digit-representing pulse at thefirst only of a number of successive digit intervals. One form of such asignal is shown in diagram (a) Fig. 6 Where the binary digit l issignalled by the presence of a negative-going pulse during the first siXmicroseconds of a ten-microsecond digit interval time. The binary digit"0 is signalled by the absence of such a pulse during any digit intervaltime.

Under these circumstances, the analogue sum deriving circuit ASDC will,during the first digit interval time l1, provide an output pulse on lead10 having an amplitude value of fourteen units. This amplitude levelwill not pass the amplitude discriminator circuit ADCS and inconsequence the gate circuits GC7 GCI@ will not be opened and no delayedinput pulse will be fed hack to the input lead lLSl of the analogue sumderiving circuit ASDC. Such output pulse of fourteen units amplitudewill, however, pass the amplitude discriminator circuit ADC4 since thereis no subtraction input on the other input lead 39 to this circuit andan output signal will therefore be provided on lead 19t This signal willserve to open the gate circuits GC/i, GCS and G05 and will also cause apulse to he fed back to the input lead H30 of the analogue sum .derivingcircuit ASDC through the delay circuit BCS so as to arrive after a delayof three digitinterval periods, i. e. during the fourth digit intervalt4, Fig. 6 (n). The opening of gate `circuits GC4 GCt causes theeffective subtraction of eight amplitude units from the available inputto each of the remaining amplitude discriminator circuits ABC3, ABC?.and ABL?L which are of lower discrimination level.

The resultant or summation input to the amplitude discriminator circuitABC3 will therefore be the original output on lead 10, i. e. fourteenunits minus the e ht unit subtraction `output from gate circuit GCE,giving a resultant amplitude of six units only. This input is, however,still greater than thc three and half unit discrimination level of thecircuit and there ".vill in consequence be an output signal on lead 18which in turn will operate to open gate circuits CCS and f-CZ and alsoto cause a pulse to be fed haci-i through delay t BC?. to the input leadILZSt of the analogue sum deriving circuit ASBC arriving at the latterafter a delay of two digit interval time periods, i. e. during intervalz3. 6 n). The opening of gate circuits @C3 'and GCE causes the etlectivefur-ther subtraction of four amplitude units from the available linputto each of the remaining ampli- -tud'e discriminator circuits ABC2 andABCL The resultant or summation input to the amplitude discriminatorcircuit ABC2 is ytherelore that of the original output on lead 1), i. e.fourteen units, less the eight unit subtraction :output from gatecircuit GCS, less the four unit subtraction output from gate circuitGCS, giving a resultant `summation level of two units only. This levelagain is greater than `the one and -a half unit discrimination level ofthe circuit and an output signal will be provided on lead 17 and this inturn will open the gate circuit GCI and also cause a pulse to be fedthrough delay circuit DC to the input lead ILZS of the analogue sumderiving circuit ASDC so as to arrive at the latter in the nextfollowing digit interval, i. e. during interval time z2, Fig. 6 (a).

The opening of gate circuit GCil causes the further subtraction of twoamplitude units `from the available input to the remaining amplitudediscriminator circuit ADCI so that the resultant input to ithe latter isthe original fourteen unit amplitude signal on lead l less fthe eightunit subtraction signal from gate GC4, less the four unit subtractionsignal from gate GC?. and less the two unit subtraction signal from gateGCT.. The summation level to circuit ADCI is therefore zero `and inconsequence during the current, i. e. the first, digit interval il ofythe output pulse train there will be no l representing output pulsesignal on the output lea-d 16. This is indicated lat a in Fig. 6 (IJ).

During the next following digit interval z2 of the pulse trains, theinput pulse signal trains on the 27 input leads IL1 LZ of the analoguesum deriving circuit ASDC themselves contain no further l digitrepresenting pulse signals `and the fed-back pulse arriving on inputlead lLZ from the discriminator ABC2 through the delay circuit DCI willbe the only input pulse available during that digit interval. Inconsequence the output pulse on lead it) will have an amplitude level ofone unit only.

Such unit amplitude level is obviously insufhcient to pass any of theamplitude discriminator circuits except that of ADCl and as the latterwill not `be affected by any ysubtraction inputs in view of thenon-opening of any of the gates GCl, GCZ, GC4, GC7 such one unit signalwill be greater than the one-half unit discrimination level of thecir-cuit ADCl and will appear as 'a 1 representing output pulse on thelead 16, i. e. a pulse appearing in the digit interval t2 as shown atbin Fig. 6 (b).

During the next or third digit interval I3 of the input pulse trains thefed hack pulse arriving on input lead IL29 of the analogue sum derivingcircuit ASDC will again ibe the only pulse existing at the time on anyof the input leads to circuit ASDC and the output on lead 1li will againbe a pulse of single unit amplitude only. This output pulse will againbe effective to pass only the amplitude discriminator circuit ADCI toprovi-de on lead 16 a second l representing output pulse during thethird digit interval t3 of the pulse train as shown -at c in Fig. 6 b

(ln)the next following digit interval t4, `Fig. 6 (a), the pulse fedback from amplitude discriminator circuit ADC4 through delay circuit DC3will larrive at the analogue sum deriving circuit ASDC on input leadl'il and since it is again the only input pulse `existing at that timethere will again be a unit amplitude output pulse on the lead it) andthis will be eiective -only to pass the amplitude disci'iminator circuitADCi to provide a third l representing output pulse on lead i6 duringthe digit interval t4 as shown at d in Fig. 6 (b).

ln the next following digit-interval t there is no input on any of the`leads IL IL27 while there are no delayed inputs still to be applied andso far as the initial fourteen simultaneous input `signals are concernedthe adding operation will now be completed. The resultant output signalon lead 16 is therefor Olll (reading from left to right) and it will beseen that this correctly represents the binary sum number S of the inputnumbers.

It will be appreciated that, had any or all of the various 6 inputsignal trains on the leads ILI 11.27 also con-A tained 1 representingsignals in any of the following digit intervals t1, l2 in, these wouldautomatically have taken part in the subsequent carry-over steps and theoutput Isignal would have been modified accordingly.

Analogue sum deriving circuit ASDC Fig. 2 `shows one circuit arrangementsuitable for constituting the analogue sum deriving circuit ASDC ofFig. 1. This circuit arrangement, which bears some resemblance to thegeneral form of circuit described in the aforesaid copending applicationNo. 105,352, comprises a first thermionic valve 33 arranged inconjunction with `a second thermionic valve 34 in the form of an anodefollower type of feed-back circuit. The valve 33 coinpiises `a pentodeof high mutual conductance value, conveniently provided by fourparallel-connected valves type EFSO. The cathode 35 and suppressor grid36 of the valve are connected to earth while the screen grid 37 isconnected to a source of positive potential +300 v. The anode 38 ofvalve 33 is connected by way ol. load resistor 39 (15 kilohms) to asource of positive potential +450 v. The anode 3S is 'also coupled by adirectcurrent circuit to the control grid 40 of valve 34 suoli circuitincluding resistor 41 (22() kilohms) shunted by capacitor 42 (270micro-microfarads). rPhis resistor/ condenser network forms part of apotentiometer chain including resistor 43 (560 kilohms) connected at itsfree end to a source of nega-tive potential 150 v. The junction betweenresistors 41 and 43 is connected to the control grid 40 of valve 34lthrough grid stopper resistor 44 (100 ohms).

The valve 34, which operates as a cathode Eollower, is also of pentodeform and conveniently comprises two parallel-connected valves, typeVC173. This valve has its anode, suppressor grid and screen gridstrapped together to provide a triode connection with inter-posedsuppressing resistors 45 (each l0() ohms). This 4anode connection isLrgnected directly to the source of positive potential The cathode 46 ofvalve 34 is connected by way of cathode load resistor 47 (33 kilohms) tothe source of negative potential -150 v. The cathode 46 is alsoconnected to lead 10 which constitutes the output lead of Fig. 1 whileSuch cathode is also coupled by way of a 'feedback path comprisingresistors 48 and 49, whose value (r ohms) will be discussed later, tothe control grid 5d of valve 33. The resistors 48 and 49 areconveniently shunted by capacitor 51 whose value (c micro-microfarads)will also be discussed later.

The control grid of valve 33 is connected to the anode of each one ofthirty-one similar diodes 52 which each form one of a pair of diodes inconjunction with thirty-one similar diodes S3. The anode of each one .jof these other diodes 53 of each pair is connected to one or other ofthe various input leads ILL lL?. 1L31 of Fig. l. The oathodes of the twodiodes 52, 53 of each pair are interconnected and joined to one end of ableed resistor 54 whose value (R ohms) will be discussed later and whoseopposite end is connected to the source of negative potential v.

in the operation of this circuit, the various input signals on any ofthe input leads llLlt 1L27 or the further input leads lLZB lL31 have aform resembling that shown in diagram (a) Fig. 6 whereby they normallyhave a resting or binary 0 representing level of, say +3 v. and wherebyany binary l digit is represented by a square negative-going pulse of,say, -15 v. amplitude.

Each diode pair performs `a switching operation and, for simplicity, oneIdiode pair only, that associated with the input lead IL1, will first beconsidered. Whenever the signal potential on the input lead ILl is inits resting condition of -j-3 v., the diode 53 alone is conductive sincethe anode of the other diode 52 which is connected area-,sor

to the control grid 50 of valve 33 is necessarily held at or below earthpotential by reason of the earthed cathode of such valve 33 and theassociated anode follower circuit. ln consequence there will be acurrent flow to the negative source, -150 v., through the associatedresistor 54 of that diode pair, of a given value of the order of Where Ris the particular resistance value assigned to the resistor 54. Wheneverthe input lead IL1 is supplied with a negative-going or l representingpulse as shown in Fig. 6 (a), the anode of the diode 53 will be drivennegatively to -15 v. and in consequence the cathodes of the two diodeswill drop in voltage to a level which is suiiicient to render the otherdiode 52 conductive; the diode 53 connected to the input lead lLl thenbecomes cut ofi.

In consequence of this action the previous current flow to the negativesource 150 v. through the resistor 54 will now talee place through theother diode 52 and will be drawn from the cathode point of valve 34through resistors 48, 49. This is in consequence of the well knownmanner of the anode follower circuit wherein any tendency for thecontrol grid of valve 33 to change in potential is resisted by thefeedback connections from valve 34 and the sequence of events issubstantially as follows. The connection of the particular resistor 54to the control grid t) of valve 33 tends to drive such control gridnegatively. This in turn results in a positive swing at the anode 38 ofvalve 33 which accordingly tends to drive the control-grid 46 of valve34 positively with resultant increased anode current flow anda rise ofpotential at the cathode 46 of the valve. This provides an increase inthe value of bleed current flow through resistors 48 and 49 equal to theextra current called for by the opening up of the diode 52.

The operation of each' of the other :diode pairs is precisely similarand as -a result the potential at the cathode` 46 of valve 34 moves-insteps and has an amplitudev N which is dependentv solely upon the numberof the thirty-one similar input diode pairs 52, 53, having input leadswhich are receiving negative l representing pulses at the same time. Theoutput on lead :is

accordingly a positive-going pulse offan'arnplitude whichisrepresentative of the analogue sum of the input pulses supplied to thecircuit. Various representative output pulses are shown in diagram (c)of Fig. 6, the irst pulse (g) being of two units amplitude, the second(l1) of ten units amplitude, the third (i) of four units amplitude, thefourth (j) of one unit amplitude and the ft'h (k) of twelve unitsamplitude.

The value, R ohms, of each of the resistors 54will determine the currentdrawn from the control grid 50 for each unit input and this, in turn andin conjunction with the combined value, 1' ohms, of the resistors 4S,49, will determine the voltage step on the output lead 1i) for each unitinput. For ease and reliability of operation, as large an output voltagestep as possible is desirable but in conflict to this is thedesirability of limiting the total swing at the cathode 46 of valve 34to a manageable amount and also to limit the current flow as much aspossible in. order to obtain maximum operating speed. described, R isgiven the value of 400 kilohms and r a value of kilohms. The variableresistor 49 is provided to facilitate the somewhat critical adjustmentofy the value r ohms. The value c of the capacitor 51 is determinedexperimentally and is such as will'make the anode follower circuitcritically damped. Avalue of l5 micro-microfarads is approximatelycorrect.V

Amplitude discrmnator circuit ADC5 A suitable circuit arrangement for'thesingle input ln the particular practical embodiment being amplitudediscriminator circuit ADCS of Fig. l is shown in Fig. 3 and comprises atirst thermionic valve 55 arranged with a second thermionic valve 56 inan anodefollower type circuit. The valve 55 is `a pentode, convenientlytype EFSO, with its cathode and suppressor grid connected directly toearth and its screen grid connected to a source of positive potentialvariable between O and 300 v. The anode of valve 55 is connected to asource of positive potential 30G v. through `anode load resistor 57 (33kilohms) and is also connected by way of a direct-current circuit to thecontrol grid of valve 56, such circuit including a resistor 58 (150kilohms) shunted by capacitor 59 (47 micro-microfarads). The resistor 58forms part of a potentiometer network with resistor 60 (150 kilohms)connected at its other end to a source of negative potential -lSO v. Thejunction of resistors 5S and 66 is connected to the control grid ofvalve 56 through grid stopper resistor 61 (100 ohms).

The anode, suppressor grid and screen grid of valve 56 (type CV173) arestrapped together to give a triodeconnection and this is connecteddirectly to the source of positive potential 300 v. The cathode of valve56, which is arranged as a cathode follower, is connected to a resistiveload which includes two series connected resistors 62 and 63 (each 180ohms) and a further resistance 64 (5 kilohms) connected at its free endto the source of negative potential v. The cathode of valve 56 isconnected to the cathode of a first diode 65' while the junction betweenresistors 63 and 64 is connected to the anode of a second diode 66. Theanode of diode 65 and cathode of diode 66 are interconnected and coupleddirectly to the control grid 67 of valve 55 while the junction betweenresistors 62 and 63 constitutes the output connection of lead 20, Fig.l.

The control grid 67 of valve 55 is connected to the terminal 15 (whichis supplied from the lead 10 and the circuit ASDC) by way of resistance69 shunted by capacitor 70. The control grid 67 is also connected to thesource of negative potential 150 v. by way of resistor 68 whose value isconveniently adjustable for initial setting-up purposes. The resistor 69has the value r ohms, i. e. l5 kilohms in the particular example whilethe capacitor 70 has the value c already discussed. The resistor 68 isrequired to pass a bleed current equal to fifteen and one half timesthat of any one of the resistors 54 of Fig. 2 and is accordingly equalto R/l51/2, i. e. 25.8 kilohms in the particular example.

In the operation of this arrangement, the anode-follower circuitconnection of valves 55, 56 will cause the control grid 67 of valve 55to remain at a substantially fixed voltage while the current flow to thegrid 67 from its connection to lead lil through resistor 69 will dependupon the voltage amplitude N of the output from the circuit ASDC. As thecurrent iiowing out through the resistor 68 to the source of negativepotential -150 v. is predetermined at 151/2 units, the Voltage at thepoint x, i. e. the output lead 20, will tend to move either negative orpositive-to compensate for any excess or deficiency of the currentiiowing in through resistor 69 over or under that flowing through theresistor 68.

If the current iiowing in through resistor 69 is exactly equal to thecurrent iiowing out through resistor 68, no current will be required tobe provided or taken by the cathode circuit of valve 56 and the voltageat point x will be equal tothat of the control grid 67. ri`he two diodes65, 66 will then be biased off by the space current of valve 56 owingthrough the resistors 62, 63. This condition corresponds,of course, toan amplitude N of the output from the analogue-sum deriving circuit ASDCof 151/2 units and is one which is only transitory in character existingduring movement of the output amplitude N between 15 `and 16 units orvice-versa.

if the output amplitude N is increasing above 151/2 units, the resultantpositive movement of the control grid 67 causes the point x to movenegative until the upper diode (i begins to conduct and thus to absorbthe requisite compensatory current from the control grid 67. Con`versely, if the output amplitude N is decreasing below lSVz units thegrid 67 of valve S5 will tend to move negatively with a resultantpositive movement at the point x whereby the lower diode 66 begins toconduct in order to supply the requisite compensatory current to 'thecontrol grid 67.

In the intermediate region where both diodes 65', 67 are cut-off thefeedback path of the anode-follower circuit is elfectively broken andthe ampliiier gain from control grid 67 to the output point x is high.l'n consequence the balance is sharp. When either diode conducts thegain from control grid 67 to point x is abruptly reduced and the voltageat point x need move by only a minute amount to compensate for largechanges in the input amplitude N. The output lead 20 is thus suppliedwith a negative-going pulse which lasts for as long as the amplitude Nof the input pulse on lead .tti exceeds 151/2 units. The pulse amplitudeis determined by the potential drop across the resistors 62, 63.

Amplitude discrimnator circuit ADC4 The form of the remaining amplitudediscriminator circuits is very slightly different from that of thecircuit ADCS dealt with above due to the incorporation of thegate-controlled subtraction inputs. One suitable form of the two inputamplitude discriminator circuit ADCd and its associated gate circuit GCNis shown in Fig. 4. This circuit comprises valves 72 and 73 arranged inan anodefollower type circuit exactly similar to that of valves 55, S ofFig. 3. The various circuit components are of identical form and valueand will not, therefore, be further described.

The input terminal 14, which is supplied from the output lead il@ of theanalogue sum deriving circuit ASDC, is connected to the control grid 71of valve 72 by way of resistor 74 (r ohms) and the latter is shunted bydamping capacitor 75 (c micro-microfarads). The control grid 71 isconnected to the source of negative potential 150 v. by way of resistor79 which forms the counterpart of resistor 63 of Fig. 3. As, in thisparticular discriminator circuit, the discrimination level is requiredto be equal to 71/2 input amplitude units, the value of this resistor 79is R/7.5, i. e. 53.3 kilohms.

The control grid 71 is also connected to the anode of a diode 77 whichforms one of a pair of diodes constituting the gate circuit GC10. Theother diode 76 has its anode connected to the lead 2d carrying theoutput from the amplitude discriminator circuit ADCS. The two cathodesof the diodes 76, 77 are interconnected and joined to a resistor 78which is connected at its opposite end to the source of negativepotential 150 v. As will be explained later, the function of this gatecircuit is, eiectively, to increase the amount of bleed current from thecontrol grid 71 to the source of negative potential 150 v. by 16 inputamplitude units and the value of the resistor 7S is accordingly R/ 16,i. e. 25 kilohms.

The operation of this circuit, ignoring for the moment the `additionalsubtraction input, is substantially identical with that alreadydescribed for the circuit ADCS, any change of `the input voltage`amplitude N on lead 10 from seven input units to eight input units orvice-versa causing an abrupt change, by a predetermined amount, of thecathode potential of valve 73 with consequent generation of `anegative-going pulse on the output lead 19 during the period when theaforesaid input on lead 10 is above seven and one-half input units inamplitude. The normal resting potential on lead 20 when the amplitudediscriminator circuit ADCS is not providing an output, due to its inputbeing below its discrimination level, is several volts positive to earthpotential and as a result the diode 76 is conductive whereas the diode77 is cut-off due to its anode being rather lower in potential amplitudeunits accordingly ows through the resistor 78 to the source of negativepotential -150 v. from the lead 20. When, however, the circuit ADC5 isoperated by Ian input exceeding its discrimination level, the resultantnegative pulse on lead 20 lowers the potential of the `anode of diode 76and the potential of the interconnected cathodes of `the two diodes 76,77 accordingly drops until diode 77 becomes conductive and diode 76 iscut-0E. When this occurs the previous sixteen unit bleed current throughresistor 78 is now drawn through diode 77 and is added to the seven andone-half unit bleed current already drawn from the control grid 71 byway of resistor 79. As `a result the previously described changeoverrange, instead of being between seven and eight `input units of voltageamplitude N on lead 10, is now between twenty-three and `twenty-fourunits and an input `amplitude N on lead iti of this value is necessarybefore the output pulse previously described is generated at the cathodeof valve 73 and made available on output lead 19. Thus, effectively, asubtraction of sixteen units from the input amplitude N has .been madealthough such subtraction has actually been achieved by increasing thediscrimination level of the circuit ADCdi. Such alternative manner ofeffecting the requisite change is to be construed as included within theterm subtraction where used in this connection within the presentspecification.

The remaining amplitude discriminator circuits ADCS `and ABC2 `aregenerally similar to that described in connection with Fig. 4 with ltheaddition of, in the case of circuit ADC3, one additional double diodegate circuit and in the case of circuit ABC2, two further double diodegate circuits each provided with appropriate value ybleed resistorsproportioned in a manner which will be self-evident from the abovedescription.

Amplitude dscrimirmtor circuit ADC] Fig. 5 shows a suitable circuitarrangement for the final `live input discriminator circuit ADCI whichprovides the sum-representing output pulse train on lead 16. Thiscircuit comprises two thermionic valves 8l `and 32 arranged in an anodefollower type circuit identical with that already described inconnection with valves 55 and 56 of Fig. 3.

The control grid of valve di is connected by way of resistor 83 (r, 15kilohms) to the input terminal l1 through which the `output `on lead l)from the analogue sum deriving circuit ASDC is received. This resistorS3 is preferably shunted by a condenser (c micromicrofarads) as in theearlier circuits. =The control grid of valve 3l is also connected by wayof bleed resistor to the source of negative potential 150 v. Thisresistor is required to provide a bleed current equivalent to thediscrimination level of one-half input amplitude unit. :its value isaccordingly R/ 0.5 or 2R, i. e. 800 kilohms.

To deal with each of the subtraction inputs already referred to, thereare provided four separate pairs of diode valves 84, 85; `87, $8; 9i),9i and 93, 9413. The diode pair 84, 85 constitute the gate circuit GC7.The anode of diode 34 is connected to lead 26 which is supplied with theoutput from the amplitude discriminator circuit ADCS while the anode ofthe other diode S5 of this pair is connected to the control grid ofvalve 8l. The cathodes of each of the diodes are interconnected andjoined to a resistor S6 which is connected at its other end to thesource of negative potential v. This resistor is required to provide acontrolled bleed current equivalent to sixteen input amplitude units andis accordingly of a value R/ 16, i. e. 25 kilohms.

-ln similar manner in the diode pair of S7, 88 constituting the gatecircuit G04, the anode yof diode 87 is connected to lead 19 suppliedwith the output from the amplitude discriminator circuit ADC4 while theanode than its cathode. A bleed current equal to sixteen input 75 of theother diode 88 of the pair is c-onnected to the aragon? l1 control gridof valve 871. The cathodes of these two diodes are interconnected andjoined to resistor 89 which is connected at its other end to the sourceof negative potential 150 v. This resistor, which is required to providea controlled bleed current equivalent to eight input amplitude units,`has a value R/ 8, i. e.v 50 kilohms. Again in similar manner, in thediode pair 9), 91 constituting the gate circuit G'CZ', the anode oll'diode 90 is connected to lead 18 supplied with the output from circuitADCF: while the anode of the other diode 91 is connected to the controlgrid of valve 81. The cathodes of the two diodes are interconnected andvjoined by way of resistor 92 to the source of negative potential 150 v.

This resistor 932 has Ia value of R/ 4, i. e. 10() kilohms.

lIn precisely similar manner in the gate circuit GC1 of diodes 93, 94Ythe anode of diode 93 is connected to lead 17 supplied with the' outputfrom the amplitude discriminator circuit ABC2 while the anodefof theother diode '94 is connected to the control grid of valve 81. Thecathodes of the two diodes are interconnected and joined by way ofresistor 95 to the source of negative potential 150 v. This resistor hasa value of R/ 2, i. e. 200 kilohms.

Each of the resistors '86, 89, 92 and 95 are conveniently madeadjustable for ease `of setting up and subsequent maintenance.

The manner of operation will be self-evident from the descriptionalready given with regard to Figs. 3 andV 4. ln the absence of anygate-opening potentials on the leads 20, i9, 18 and 117, only `theresistor 30 is operative to provide a bleed current from the controlgrid of valve 81 and the change-over operation with consequentgenera-tion of a negative-going pulse on the output lead 16 will occur'when the input voltage amplitude N on lead li) varies in the range ofbetween Zero and one input unit. Whenever any one or more of the leads17-20 are operative to open the associated gate circuit, thecorrespondingly increased bleed current made available to the controlgrid yof valve 81 shifts the change-over range accordingly to providethe equivalent of a subtraction from the input signal `amplitude N onlead 10.

The delay devices DC1, DCZ, DCS and DC/i can be of any suitable form,for instance, of the electricaldelay line type or of the supersonic, e.g. mercury, delay line type or, more preferably, they may be of thesocalled shufe circuit variety as described in Fig. 3 ot the aforesaidcopending application.

A device of the last mentioned type provides a delay of one digitinterval only but several similar devices may be arranged serially toprovide arrangenients suitable for constituting the delay circuits DCZ,DCS and DC@ of Fig. 1. l

As an alternative .to delaying of the reapplied outputs from theamplitude discriminator circuits ADC3, ADC@ and ADCS by two, three andfour digit intervals as previously described it is possible to use onlyone-digit period delay circuits and to make each of these feed inparallel an appropriate number of input leads on the amplitudesum-deriving circuit ASDC, provided there are a suftcient number ofspare input positions available on the latter. Thus, as shown in Fig. 7,with an analogue sumderiving circuit ASDC capable of dealing withthirty-one separate inputs. only sixteen input leads IL1-L16 are usedfor supply from possible internal sources and the remaining fifteeninput leads IL17-1L31 are supplied from the amplitude discriminat-orcircuits ADC5, ADC4, ADCS, ABC2. The output from amplitude discriminatorcircuit ADCS, which is equivalent to the carry back of decimal value 16,is delayed by one digit period in delay circuit DC4 and then appliedsimultaneously to eight input leads ILM-H31. Similarly the' output fromamplitude discriminator circuit ADC4, equivalent to a carry back ofdecimal value 8, is appliedthrough a single digit period delay circuitDCS to four input leads IL20 lL23 in parallel while in precisely similarmanner inV value of the associated resistor 54 (Fig. 2) to one eighth,v

`one quarter or one half of its normal value of R ohms.

An arrangement as described above has a number of obvious applicationsin electronic circuits dealing with binary numbers which are representeddynamically in pulse signalv form while it is also capable ofWiderapplication by appropriate rearrangement of the parts and choice ofcomponentvalues. The number of parallel or simultaneous inputs may bevaried as desired with appropriate alteration of the number of amplitudediscriminator circuits and associated gate-controlled subtraction inputsand delayed feed-back signals. Thus a fteen input analogue sumV derivingcircuit, affording twelve inputs for receiving external signals wouldfeed four amplitude discriminator 'circuits similar to those of ADC,ADCZ, ADC3 and ADC4 just described except for the elimination of lthesixteen unit subtraction input and the associated gate circuits GC7 GCM)together with the delay circuit-DC4; A seveninput arrangement, providingfor ve external signals could be devised on simil'ar lines. The numberof parallelA inputs which can be used is theoretically infinitey but inpractice the necessity of proportioning the various resistors, whosevalues have been dealt with in detail, in order to provide the requisitespeed and reliability of operation, sets a practical limit which is ofthe order of 31 or, at the most, 63 simultaneous inputs when digitssignalling speeds of the order of 100 kc. per second are required.

One particular application of the invention is to use in conjunctionwith a binary number multiplying arrangement ofV the kind described incopending patent application Serial No. 132,579. This application isillustrater in block schematic form in Fig. 8 of the drawings. Thisparticular multiplier arrangement is one in which one of the numbers tobe multipliedfe. g. the multiplicand D, is

` fed'in asa-serial pulse train onllead M andpasses through a series ofdelay devices D1, D2 Dn, each imposing a delay equal to one digitperiod'of the pulse train. Between each delay device and before thefirst delay device is connected a lead passing through a gate circuitGti, Gl, G2 Gn to a separate one of the various input leads lLl ILn of amultiple input adding device MIAD as described above. These gatecircuits Gt), G1 Gn are arranged to be set up respectively in their openor closed states in accordance with the particular significance of theappropriate digits R0, R1 Rn of ja second number to be multiplied, e. g.the multiplier R. in the operation of the arrangement the various digitsof the rst number M either pass or do not pass, in accordance with thesignificance of the appropriate digit 'of the second number R, to themultiple input adding circuit MlAD in their progressively increasedbinary values as they emerge from the respective unit delays D1 Dn.. Acircuit of this kind embodying an adding arrangement according to thepresent invention is materially simpler than that which is obtained whenother adding circuits are used in such multiplier devices.

We claim:

l. An arrangement for effecting simultaneous addition of not more than2"-n binary numbers each separately represented by simultaneouslyyoccurring electric pulse signal trains which comprises sum pulsederiving means having not more than 2"-k l4 input terminals aridf anoutput terminal, means for applying said input pulse signal trains oneto each of not more than 2-11 of said input terminals, said sum pulsederiving means providing at said output terminal during each digitinterval of said input pulse trains a single output pulse Whoseamplitude is representative of the analogue sum of the total number ofbinary l-digit representing signals occurring simultaneously in saidinput pulse signal trains, a lirst amplitude discriminator circuithaving an input terminal and an output terminal, circuit means forapplying the output signals from said output terminal of said sum pulsederiving means to said input terminal of said first amplitudediscriminator circuit, said first amplitude discriminator circuitproviding an output signal at its output terminal only when theamplitude of the input signal at its input terminal is representative ofat least 21 simultaneous 1-digit representing signals in said inputpulse trains, n-l further amplitude discriminator circuits each havingan input terminal and an output terminal, circuit means for applying theoutput signals from said output terminal of said sum pulse derivingmeans to each of said input terminals of said further amplitudediscriminator circuits, each of said further amplitude discriminatorcircuits having signal controlled amplitude reducing means for reducingthe effective amplitude of the input signals applied to its inputterminal by a predetermined amount, the rst of said further amplitudediscriminator circuits having a single amplitude reducing controlterminal eiective, when energised, to reduce the amplitude of the signalat its input terminal by an amount equal to 2"-1 'ldigit representingsignals in the input signal trains and providing an output signal at itsoutput terminal only when the resultant amplitude of its input signalless any applied reduction is representative of at least 2"2simultaneous l-digit representing signals, the second of said furtheramplitude discriminator circuits having two amplitude reducing controlterminals effective respectively, when energised, to reduce theamplitude of the signal at its input terminal by amounts equal to 2-1and 2*2 l-digit representing signals in the input signal trains andproviding an output signal at its ouput terminal only when the resultantamplitude of its input signal less any applied reduction isrepresentative of at least 2"3 simultaneous l-digit representingsignals, any further of said further amplitude discriminator circuitshaving three, four n-l amplitude reducing control terminals respectivelyand `each effective respectively to reduce the amplitude of the signalat the input terminal of such circuit by amounts equal to 2*1' 2-2 21simultaneous .ldigit representing signals in the input signal trains andproviding an output signal at the output terminal of such circuit onlywhen the resultant amplitude of its input signal less any appliedreduction is representative of at least 2-4 20 simultaneous lrepresenting signals, n-l delay devices each having input and outputterminals, the rst of said delay devices imposing a delay equal to rz-ldigit intervals of the input pulse signal trains, the second of saiddelay devices imposing a delay equal to 1z-2 digit intervals of saidinput pulse signal trains and the remaining delay devices similarlyimposing delays equal respectively to n-3 l digit interval of said inputpulse signal trains, circuit means connecting the output terminals ofeach of said delay devices to separate ones of the further n-l inputterminals of said sum pulse deriving means, circuit means connecting theoutput of said first amplitude discriminator circuit to the inputterminal of said iirst delay device and to each oi the amplitudereducing control terminals of the further amplitude discriminatorcircuits which are effective to reduce the signal amplitude of suchcircuits by amounts equal to 21 l"di git representing signals, circuitmeans connecting the output terminal of said tirst of said furtheramplitude discriminator circuits to the input terminal of said seconddelay device and also to each of the amplitude reducing control termi--nais of said further amplitude discriminator circuits which areer'ective to reduce the signal amplitude by 271-2 ldigit representingsignals and similar further circuit means connecting the outputs of theremaining further amplitude discriminator circuits except that having anamplitude discrimination equal to one (2) ldigit representing signal tothe remaining delay devices in order and also to the amplitude reducingcontrol terminals ot' such further amplitude discriminator circuitswhich are eiective respectively to reduce the amplitude of the inputsignal by 2*3 21 1-digit representing signals, the output terminal ofsaid further amplitude discriminator circuit having an amplitudediscrimination level of one (20) l"digit representing signal providingan output signal representing in serial pulse train form similar' to theinput pulse signal trains, the binary sum of the numbers simultaneouslyrepresented by such input pulse signal trains.

2. An arrangement for effecting addition of `a plurality of binarynumbers each represented in serial form by simultaneously occurringelectric pulse signal trains which comprises sum pulse deriving meanshaving a plurality of separate input terminals for connection. `one toeach of the sources of simultaneously occurring input signal trains andan output terminal at which is provided a signal pulse whose amplitudeis representative of the analogue sum of the number of ldigitrepresenting signals occurring simultaneously at said input terminals,a. plurality of amplitude discriminator circuits each having an inputterminal iand an output terminal and providing an output signal pulse atsaid output terminal only when the resultant amplitude of the inputsignal applied thereto exceeds a predetermined discrimination level, therespective discrimination levels of said amplitude discriminatorcircuits being diiierent and of progressively decreased values `relatedto the different binary power values 2", 2 21, 20, each of saidamplitude discriminator circuits except the rst which has the highestamplitude (2") discrimination level including amplitude subtractingmeans having control signal terminals and controlled by signals `appliedto such control signal terminals for reducing the effective amplitude ofan input signal pulse applied to its input terminal from said sum pulsederiving means by amounts related to the dilerent binary power values ofamplitude discriminator circuits of higher discrimination level thanitself, a plurality of delay devices each having input and outputterminals and each having successively greater delay times equal todifferent integral numbers of the digit interval times of the appliedpulse sign-al trains, circuit means connecting the output terminal ofsaid sum pulse deriving means to the input terminal of each of saidamplitude discriminator circuits in parallel, circuit means connectingthe output terminal of said amplitude discriminator circuit of highest(2) discrimination level to the input terminal of said delay means ofhighest delay time and to control signal terminals of the arnplitudesubtracting means of said amplitude discriminator circuits of lowerdiscrimination level to control subtraction therein of an amplitudedetermined by the` discrimination level of said iirst discriminatorcircuit, similar circuit means connecting the output terminal of theamplitude discriminator circuit of next lowerl (2n-1) discriminationlevel to the input terminal of said delay means of next lower delay timeand to control. signal terminals of the amplitude subtracting means ofsaid amplitude discriminator circuits of lower discrimination level thanitself to control the subtraction therein of an amplitude determined bythe amplitude discrimination level of said second amplitudediscriminator circuit and further similar circuit means connecting theoutput terminals of each of said further `amplitude discriminatorcircuits of lower discrimination levels except that of the lowest (20)discrimination level to the input terminals of said other delay meansand to the control signal terminals of the amplitude subtracting meansof the `amplitude discriminator circuits of lower discrimination levels,circuit means connecting the output terminals' of cach of said delaymeans to separate input terminals of said sum pulse deriving means and1an output connection from the output terminal of sadamplitudediscriminator circuit of lowest discrimination level for providing apulse signal train representative of the binary sum of the numbersrepresented by the pulse signal trains applied simultaneously to thesaid separate input `terminals of said sum pulse deriving means.

3. An arrangement according to claim 2 wherein said amplitudediscriminator circuits each comprise a thermionic valve circuit of theanode follower type, means for causing a flow of bleed current to orfrom the input of said circuit which is variable in accordance with theamplitude of the applied sum-representing pulse and further' means forproviding ya flow of bleed current from or to said input of said circuitwhich is constant and which is predetermined in accordance with therequired discrimination level.

4. An arrangement according to claim 3 wherein those amplitudediscriminator circuits which are required to modify the effectiveamplitude of the input sum-representing puise are provided with currentaltering means, controlled by the output signal of another amplitudediscriminator circuit, for adding to the value of said constant andpredetermined value of bleed current from or to said input of saidanode-follower circuit.

5. An arrangement according to claim 4 wherein the anode-follower typecircuit includes a cathode follower final stage and a feedback circuitbetween the cathode output circuit of such nal stage and the controlgrid of the 'first input stage which includes parallel paths through twomutually reversed polarity diodes connected to spaced 'tapping points onthe cathode load impedance of such final stage.

6. An 'arrangement according to claim 5 in which the output connectionfrom such amplitude discriminator circuit is taken from the mid point ofthat portion of the cathode load impedance lying between said tappingpoints.

7. An arrangement according to claim 2 wherein said sum pulse derivingmeans comprises a thermionic valve circuit of the anode follower type`and a plurality of switching means each controlled by one of said inputpulse trains and a source of bleed current, said switching means eachcontrolling the iiow of 'a predetermined unit of bleed current in theinput circuit of said anode follower circuit.

8. AnV arrangement accordingl to claim 7 wherein each of said switchingmeans comprises a pair of diodes arranged in an and type gate circuitand a resistor of predetermined valu'e in series with said gate circuitbetween Yth'c input control grid of the first valve of said anodefollower circuit 'and the negative terminal of said source of bleedcur-rent.

9. A circuit arrangement for generating an output potential whoseamplitude value is directly proportional to the number of a plurality ofseparate input leads which are supplied with a chosen energisingpotential at any one instant which comprises an anode follower typecircuit including a iirst'input amplifier valve and a second cathodefollower ouput valve l). C. coupled together and a feed back pathincluding a series resistance between the cathode of said second valveand the control grid of said first valve, a plurality of input gatedevices controlled respectively by the energisi-ng potential on adifferent one of said Yinput leads7 a plurality of bleed resistances ofpredetermined value, a source of potential which is different from' thatof the cathode of. said first valve, and circuit means for connectingeuch of said gate devices in series with a different one of said bleedresistances between said control grid of said first valve and saidsource of potential whereby the number of said bleed resistances whichare connected in parallel between said control' grid of `said rst valveand said source of potential at any one instant is determined by thenumber of said input leads which are supplied with energising potentialat that instant.

l0. A circuit arrangement for providing a signal indication whether avariable input potential is above or below a predetermineddiscrimination level which comprises an anode follower type thermionicvalve circuit including an input amplifier valve and a D. C. coupledcathode follower output valve having a cathode load resistance and 'acurrent feedback path between the cathode circuit of said output valveand the control grid of said input Valve, a resistance between thesource of said variable input potential andthe control grid of saidinput valve to provide a variable value bleed current to or from saidcontrol grid, a second resistance connected between said Vcontrol gridanda source of potential of polarity, relative to said control grid,which is opposite to that of said variable input potential, said secondresistance being of a value predetermined in accordance with therequired discrimination level to provide a constant value of bleedcurrent from or to said control grid and said current feedback pathincluding parallel but mutually reversed polarity diodes respectivelyconnected to spaced tapping points on said cathode load of said cathodefollower valve whereby the cathode potential of such cathode followervalve undergoes an abrupt change whenever the bleed current due to saidinput potential becomes either greater than'or less than said constantvalue bleed current.

ll. An arrangement for effecting simultaneous addition of not more thanfive binary numbers each separately represented by simultaneouslyoccurring electric pulse signal trains, which comprises sum pulsederiving means having not more than seven input terminals and an outputterminal, means for applying said input pulse signal trains one to eachof not more than `live of said input terminals, said output terminal ofsaid sum pulse deriving means providing during each digit interval ofthe simultaneously applied input pulse signal trains a single outputsignal pulse whose amplitude is representative of the analogue sum ofthe total number of binary l digit-representing signals occurringsimultaneously in said input pulse signal trains, a first amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for supplying signal output from the output terminal ofsaid sum' pulse deriving means to said input terminal of said rstamplitude discriminator circuit, said first amplitude discriminatorcircuit providing an output pulse signal at its output pulse terminalonly when the amplitude of the signal at its input terminal is `at leastequal to that representative of four simultaneous l digit-representingsignals in said input signal trains, a second 4amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplyiug the output signal from the output terminal of said sumpulse deriving means to said input terminal of said second amplitudediscriminator circuit, first signal controlled amplitude reducing meansconnected to said second amplitude discriminator circuit and having afirst control signal terminal which, when energiscd, causes theeffective amplitude of the input signal applied to said input terminalof said second amplitude discriminator circuit to be reduced by anamount representative of four l digit-representing' input signals, saidsecond amplitude discriminator circuit providing an output pulse at itsoutput terminal only when the resultant amplitude of the signal `at itsinput terminal after any reduction is at least equal to thatrepresentative of two l digit-representing signals, a third amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for supplying the output signal from the output terminalof said sum pulse deriving means to said input terminal of said thirdamplitude discriminator circuit, second and third signal controlledamplitude reducing means each connected toV said third amplitudediscriminator circuit, said second amplitude reducing means having asecond control signal terminal which, when energised, causes theeffective amplitude of the input Vsignal applied to said input terminalof said third amplitude discriminator circuit to be reduced by an amountrepresentative of four l digit-representing input signals, said thirdamplitude reducing means having a third control signal terminal which,when energised, causes the effective amplitude of the input signalapplied to said input terminal of said third amplitude discriminatorcircuit to be reducedby an amount representative of two ldigit-representing input signals, said third amplitude discriminatorcircuit providing an output pulse at its output terminal only when theresultant amplitude of the signal at its input terminal after anyreduction is at least equal to that representative of one ldigit-representing input signal, first and second delay devices eachhaving input and output terminals, circuit means for supplying thesignal output from the output terminal of said first amplitudediscriminator circuit to said first `and second control signal terminalsand to said input terminal of said rst delay device, circuit means forsupplying the signal output from the output terminal of said secondamplitude discriminator circuit to said third control signal terminaland to said input terminal of said second delay device, circuit meansfor supplying the signal output from the output terminal of said rstdelay device to at least one unused input terminal of said sum pulsederiving means and circuit means for supplying the signal output fromthe output terminal of said second delay device to another unused yinputterminal of said sum pulse deriving means, said output terminal of saidthird amplitude discrminator circuit providing an output pulse signaltrain which is representative of the sum of the binary numbersrepresented by the simultaneously occurring input pulse signal trains.

l2. An arrangement for electing simultaneous addition of not more thanve binary numbers each separately represented by simultaneously4occurring electric pulse signal trans, which comprises sum pulsederiving means having not more than seven input terminals Iand an outputterminal, means for applying said input pulse signal trains one to eachof not more than five of said input terminals, said output terminal ofsaid sum pulse deriving means providing during each digit interval ofthe simultaneously *applied input pulse signa-l trains a single outputsignal .pulse whose amplitude is representative of the analogue sum ofthe total number of binary l digitrepresenting signals occurringsimultaneously in said input pulse signal trains, a iirst amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for supplying signal output from the output terminal ofsaid sum pulse deriving means to said input terminal of said irstamplitde discriminator circuit, said first amplitude discriminatorcircuit providing an output pulse signal at its output pulse terminalonly when the amplitude of the signal at its input terminal is at leastequal to that representative of four simultaneous l digit-representingsignals in said input signal trains, `a second amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the output signal from the output terminal of said sumpulse deriving means to said input terminal of said second amplitudediscriminator circuit, irst signal con trolled lamplitude reducing meansconnected to said second amplitude discriminator circuit yand having arst control signal terminal which, when energised, causes the effectiveamplitude of the input `signal applied to said input terminal of saidsecond amplitude discriminator circuit t-o be reduced by an amountrepresentative of four l digit-representing input signals, said secondamplitude discriminator circuit providing lan output pulse at its outputterminal only when the resultant amplitude of the signal at its inputterminal after any reduction is at least equal to that representative oftwo l digit-representing signals, a third amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the output signal from the output terminal of Said sumpulse deriving means t-o said input terminal of 18 said third lamplitudediscriminator circuit, second and third signal controlled amplitudereducing means each connected to said third amplitude discriminatorcircuit, said second amplitude reducing means having a second controlsignal terminal which, when energised, causes the effective amplitude ofthe input signal applied to said input termin-al of Isaid thirdamplitude discriminator circuit to be reduced by an amountrepresentative of four 1" digit-representing input signals, said thirdamplitude reducing means having a third control signal terminal which,when energised, causes the effective amplitude of the input signalapplied to said input terminal of said third amplitude di-scriminatorcircuit |to be reduced by an amount representative of two ldigit-representing input signals, said third amplitude discriminatorcircuit providing an output pulse at its output terminal only when theresultant amplitude of 'the signal at its input terminal `after anyreduction is at least equal to that representative of one ldigit-representing input signal, a first delay device having input andoutput terminals and imposing a delay time of signals fed thereto equalto two digitinterval time periods of said input pulse signal trains, asecond delay device having input and output terminals and imposing adelay time of signals vfed thereto equal t0 one digit-interval timeperiod of said input pulse signal trains, circ-uit means for supplyingthe signal output from the youtput terminal of said iirst amplitudediscriminator circuit to said rst and second control signal terminals:and to said input terminal of said rst delaydevice, circuit means forsupplying the signal output from the output terminal of said secondamplitude `discriminator circuit to said third control signal terminaland to Asaid input terminal of said second delay device, circuit meansfor supplying the signal output from the output terminal of said firstdelay device to an unused input terminal of said sum pulse derivingmeans and circuit means for supplying the signal output from the `outputterminal of said second delay device to another unused input terminal ofsaid sum pulse deriving means, said output -terminal of `said thirdamplitude discriminator circuit providing an output pulse signal trainwhich is representative of the sum of the binary number-s represented bythe simultaneously occurring input pulse signal trains.

13. An arrangement for effecting simultaneous addition of not more thanfour binary numbers each separately represented by simultaneouslyoccurring electric pulse signal trains, which comprises sum pulsederiving means having not more than seven input terminals and an outputterminal, means for applying said input pulse signal trains one to eachof not more than four of said input terminals, said output terminal ofsaid pulse deriving means providing during each digit interval of thesimultaneously applied input pulse signal trains a single output signalpulse whose amplitude is representative of the analogue sum of the totalnumber ot binary l digit-representing signals occurring simultaneouslyin said input pulse signal trains, a first amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying signal output from the output terminal of said sum pulsederiving means to said input terminal of said rst amplitudediscriminator circuit, said first amplitude disc' inator circuitproviding an output pulse signal at it output pulse terminal only whenthe amplitude of the signal at its input terminal is at least equal tothat representative of .tour simultaneous l digit-representing signalsin said input signal trains, a second amplitude discriminator circuithaving an input terminal and an output terminal, circuit means forsupplying the output signal. from the output terminal of said sum pulsederiving means to said input terminal of said second amplitudediscriminator circuit, rst signal controlled amplitude reducing meansconnected to said second amplitude discriminator circuit and having arst control signal terminal which, when energised, causes the effectiveamplitude of the input signal applied to said input terminal of saidsecond amplitude discriminator circuit to be reduced by an amountrepresentative of four "1 digit-representing input signals, said secondamplitude discriminator circuit providing an output pulse at its outputterminal only when the resultant amplitude of the signal at its inputterminal after any reduction is at least equal to that representative oftwo Hl digit-representing signals, a third amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the output signal from the output terminalof said sumpulse deriving means to said input terminal of said third amplitudediscriminator circuit, second and third signal controlled amplitudereducing means each connected to said third amplitude discriminatorcircuit, said second amplitude reducing ,means having a second` controlsignal terminal which, whenv energised, causes Vthe eliective amplitudeof the input signal applied to said input terminal ot said third`amplitude discriminator circuit to be reduced by an amountrepresentative of four "l digitrepresenting input signals, said third,amplitude reducing means having a third control signal ,terminal which,when energised, causes the effective amplitude of .the input signalapplied to said input terminal of said third amplitude discriminatorcircuit to be reduced by an amount representative of two ldigit-representing input signals, said third amplitude discriminatorcircuit providing `an output pulse at its output terminal only when theresultant amplitude of the signal at its inputterminal after any.reduction is at least equal to that representative of onedigit-representing input signal, first and ,second delay devices eachhaving input and output terminals and each imposing a delay time ofsignalsfed thereto equal to one digit interval time period of said inputpulse signal trains,

circuit means for supplying the signal output from the output terminalof said firstamplitude discriminator circuit to said first and secondcontrol signal terminals and to said input terminal of said first delaydevice, circuit means for supplying the signal output from the outputterminal of said second amplitude discriminator circuit to said thirdcontrol signal terminal and to said input terminal of said second delaydevice, circuitmeans for supplying the signal output from the outputterminal of said first delay device to two unused input terminals ofsaid sum pulse deriving means and circuit means for supplying the signaloutput from the output terminal Of said second delay device to anotherunused input terminal ofsaid sum pulse deriving means, said outputterminal of said third amplitude discriminator circuit providing anoutput pulse signal train which is representative of the sum of thebinary numbers represented by the simultaneously occurring input pulsesignal trains.

14. An arrangement for effecting simultaneous addition of not more thantwelve binary numbers each separately represented by simultaneouslyoccurring electric pulse signal trains, which comprises sumpulse,de1-iving means having not more than fifteen input terminals andan output terminal, means for applying said input trains one to each ofnot more than twelve of said input terminals, said output terminal ofsaid sum pulse deriving means providing during each digit interval ofthe simultaneously applied input pulse signal trains a single outputsignal pulse whose amplitude is representative of the analogue sum ofthe total number of binary l digitrepresenting signals occurringsimultaneously in Asaid input pulse signal tra-ins, a first amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for-.supplying the signal outputv from the output terminalof said sum pulse deriving means to said input terminal of said firstamplitude discriminator circuit, said first amplitude discriminatorcircuit providing an output pulse signal at its output terminal onlywhen the amplitude of the signal at its input terminal is at least equalto that representative of eight l digit-representing input signals, asecond amplitude discriminator circuit having an input terminal and anoutput terminal, circuit means for supplying the output signal from theoutput terminal of said sum pulse deriving means to Said input terminalof said second amplitude discriminator circuit, first signal controlledamplitude reducing means connected to said second amplitudediscriminator circuit and having a first controlled signal terminalwhich, when energised, causes the efiective amplitude of the inputsignal lapplied to said input terminal of said second amplitudediscriminator circuit to be reduced by an amount representative of eightl digit-representing input signals, said second amplitude discriminatorcircuit providing an output pulse at its output terminal only when theresultant amplitude of the signal at its input terminal after anyapplied reduction is at least equal to that representative of four l digit-representing input signals, a third amplitude discriminator circuithaving an input terminal and an output terminal, circuit means forsupplying the output signal from the output terminal of said sum pulsederiving means to said input terminal of said second amplitudediscriminator circuit, second and third signal controlled amplitudereducing means connected to said third amplitude discriminator circuit7said second amplitude reducing means having a second control signalterminal which, when energised, causes the etiective amplitude of theinput signal applied to said input terminal of said third amplitudediscriminator circuit to be reduced by an amount representative of eightl digit-representing input signals, said third amplitude reducing meanshaving a third control signal terminal which, when energised, causes theeffective amplitude of the input signal applied to said input terminalof said third amplitude discriminator circuit to be reduced by an amountrepresentative of four l digitrepresenting input signals, said thirdamplitude discriminator circuit providing an output pulse at its outputterminal only when the resultant amplitude of the signal at its inputterminal after any reduction is at least equal -to that representativeof two l digit-representing input signals, a lfourth amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for supplying the output signal from the output terminalof said lsum pulse deriving means to said input terminal of said fourthamplitude discriminator circuit, fourth, fifth and sixth signalcontrolled amplitude reducing means connected to n said fourth amplitudediscriminator circuit, said fourth `amplitude reducing means having afourth control signal terminal which, when energised, causes theefective amplitude of the input signal applied to said inputV terminalof said fourth amplitude discriminator circuit to be reduced by anamount representative of eight l digitrepresenting input signals, saidfifth amplitude reducing means having a fifth control signal terminal,which when energised, causes the effective amplitude of the input signalapplied to said input terminal of said fourth amplitude discriminatorcircuit to be reduced by anamount representative of four ldigit-representing input signals and said sixth amplitude reducing meanshaving a sixth rcrontrol signal terminal which, when energised, causesthe eliective amplitude of` the input signal applied to said inputterminal of said fourth amplitude discriminator circuit to be reduced byan amount representative of two l digit-representing input signals,saidfourth amplitude discriminator circuit providing an output pulseatits output terminal only when the resultant amplitude of the signal atits input terminal after any reduction is at least equal to thatrepresentative of one l digit-representing input signal, first, secondand third delay devices each having input and out-put terminals, circuitmeans for supplying the signal output fromV the output terminal ot saidfirst amplitude discriminator circuit to said first, second and fourthcontrol signal terminals and to said input terminal of 4said first delaydevice, circuit means for supplying the signal output from `the outputterminal ot said second amplitude discriminator circuit to said thirdand fifth control signal terminals and to said input terminal of saidsecond delay device, circuit means for supplying the signal output fromthe output -terminal of said third amplitude discriminator circuit tosaid sixth control signal terminal and to said input terminal of saidthird delay device and circuit means for supplying the output signalsfrom the output terminals of each of said delay devices to unused inputterminals of said pulse amplitude adding means, said output terminal ofsaid fourth amplitude discriminator circuit providing `an output pulsesignal train which is representative of the sum of the binary numbersrepresented by said simultaneously occurring input pulse signal trains.

15. An arrangement for effecting simultaneous addition of not more thantwelve binary numbers each separately represented by simultaneouslyoccurring electric pu'lse signal trains, which comprises sum pulsederivingy means having not more than fifteen input terminals and anoutput terminal, means for lapplying said input trains one to each ofnot more than twelve of said input terminals, said output terminal ofsaid sum pulse deriving means providing during each digit interval ofthe simultaneously applied input pulse signal trains a single outputsignal pulse whose amplitude is representative of the analogue sum ofthe total number of binary l digit-representing signals occurringsimultaneously in said input pulse signal trains, a first amplitudediscriminator circuit having an input terminal and an output terminal,circuit means for supplying `the signal. output from the output terminalof said sum pulse deriving means to said input terminal of said firstamplitude discriminator circuit, said first amplitude discriminatorcircuit providing an output pulse signal at its output terminal onlywhen the amplitude of the signal at its input terminal is at least equalto that representative of eight l digit-representing input signals, asecond amplitude discriminator circuit having an input terminal and anoutput terminal, circuit means for supplying the output signal from theoutput terminal of said sum pulse deriving means to said input terminalof said second amplitude discriminator circuit, first signal controlledamplitude reducing means connected to said second amplitudediscriminator circuit and having a first controlled signal terminalwhich, when energised, causes the effective amplitude of. the inputsignal applied to said input terminal of said second amplitudediscriminator circuit to be reduced by an amount representative of eightl digit-representing input signals, said second amplitude discriminatorcircuit providing an output pulse at its output terminal only when theresultant amplitude of the signal at its input terminal after anyapplied reduction is at least equal to that representative of four ldigit-representing input signals, a t

third amplitude discriminator circuit having an input terminal and anoutput terminal, circuit means for supplying the output signal from theoutput terminal of said sum pulse deriving means to said input terminalof said second amplitude discriminator circuit, second and third signalcontrolled amplitude reducing means connected to said third amplitudediscriminator circuit, said second amplitude reducing means having asecond control signal terminal which, when energised, causes theeffective amplitude of the input signal applied to said input terminalof said third amplitude discriminator circuit to be reduced by an amountrepresentative of eight l digit-representing input signals, said thirdamplitude reducing means having a third control signal terminal which,when energised, causes the effective ampli-tude of the input signalapplied to said input terminal of said third Aamplitude discriminatorcircuit to be reduced by an amount representative of four ldigit-representing input signals, said third amplitude discriminatorcircuit providing an output pulse at lits output terminal only when theresultant amplitude of the signal at its input terminal after anyrduction is at least equal to that representative of two ldigit-representing input signals, a fourth amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the output signal from the output terminal of said sumpulse deriving means to said input terminal of said fourth amplitudediscriminator circuit, fourth, fifth and sixth signal co-ntrolledamplitude reducing means connected to said fourth amplitudediscriminator circuit, said fourth amplitude reducing means having afourth control signal terminal which, when energised, causes theeffective amplitude of the input signal applied to said input terminalof said fourth amplitude discriminator circuit to be reduced by anamount representative of eight 1 digit-representing input signals, saidfifth amplitude reducing means having a fifth control signal terminal,which when energised, causes the effective amplitude of the input signalapplied to said input terminal of said fourth amplitude discriminatorcircuit to be reduced by an amount representative of four ldigitrepresenting input signals and said sixth amplitude reducing meanshaving a sixth control signal terminal which, when energised, causes theeffective amplitude ot' the input signal applied to said input terminalof said fourth amplitude discriminator circuit to be reduced by anamount representative of two l digit-representing input signals, saidfourth amplitude discriminator circuit providing 1an output pulse at itsoutput terminal only when the resultant amplitude of the signal at itsinput terminal after any reduction is at least equal to thatrepresentative of one l digit-representing input signal, a first delaydevice having input and output terminals and imposing a delay time uponsignals fed thereto equal to three digit-interval time periods of saidinput pulse signal trains, a second delay device having input and outputterminals and imposing a delay time upon signals fed thereto equal totwo digitinterval time periods of Said input pulse signal trains, athird delay device having input and output terminals and imposing adelay time upon signals fed thereto equal to one digit interval time ofsaid input pulse signal trains, circuit means for supplying the signaloutput from the output terminal of said first amplitude discriminatorcircuit to sai-d first, second and fourth control signal terminals andto said input terminal of said first delay device, circuit means forsupplying the signal output from the output terminal of said secondamplitude discriminator circuit to said third and fifth control signalterminals an-d to said input terminal of said second delay device,circuit means for supplying the signal output from the output terminalof said third amplitude discriminator circuit to sai-d sixth controlsignal terminal and to said input terminal of said third delay deviceand circuit means for supplying the output signals from the outputterminals of each of said Idelay devices to different unused inputterminals of said sum pulse deriving means, said output terminal of saidfourth amplitude discriminator circuit providing an output pulse signaltrain which is representative of the sum of the binary numbersrepresented by said simultaneously occurring input pulse signal trains.

16. An arrangement for effecting simultaneous addition of not more thaneight binary numbers each separately represented by simultaneouslyoccurring electric pulse signal trains, which comprises sum pulsederiving means having not more than fifteen input terminals and anoutput terminal, means for applying said input trains one to each of notmore than eight of said input terminals, said output terminal of saidsum pulse deriving means providing during each. digit interval of thesimultaneously applied input pulse signal trains a single output signalpulse whose amplitude is representative of the analogue sum of the totalnumber of binary l digit-representing signals occurring simultaneouslyin said input pulse signal trains, a first amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the signal output from the output terminal of saidlsumpulse deriving means to said input terminal of said first amplitudediscriminator circuit, said first amplitude discriminator circuitproviding an output pulse signal at its output terminal only when theamplitude of the signal at its -deriving means to said input terminalVofi said second amplitude discrirninator circuit, rst signal controlledamplitude reducing means connected to said second amplitudediscriminator circuit and having a first controlled signal terminalwhich, when energised, causes the effective amplitude of the inputsignal applied to said input yterminal of said second amplitudediscriminator circuit to be reduced by an amount representative of eightl digit-representing input signals, said second amplitude discriminatorcircuit providing an output pulse at its output terminal only when theresultant amplitude of thc signal at its input terminal after anyapplied reduction is at least equal to that representative of four ldigitrepresenting input signals, a third amplitude discriminator circuithaving an input terminal and an output terminal, circuit means forsupplying the output signal from the output terminal of said sum pulsederiving means to said input terminal of said second amplitudediscriminator circuit, second and third signal controlled amplitudereducing means connected to said third am 4plitude discriminatorcircuit, said second amplitude reducing means having a second controlsignal terminal which, when energiscd, causes the effective amplitude ofthe input signal applied to said input terminal of said third amplitudediscriminator circuit to be reduced by an amount representative of eightl digit-represent ing input signals, said third amplitude reducing meanshaving a third control signal terminal which, when energised, causes theeffective amplitude ofthe input signal applied to said input terminal ofsaid third amplitude discriminator circuit to be reduced by an amountrepresentative of four l digit-representing input signals, said thirdamplitude discriminator circuit providing an output pulse at its outputterminal only when the resultant amplitude of the signal at its inputterminal after any reduction is at least equal to that representative oftwo l digit-representing input signals, a fourth amplitude discriminatorcircuit having an input terminal and an output terminal, circuit meansfor supplying the output signal from the output terminal of said sumpulse deriving means to said input terminal of said fourth amplitudediscriminator circuit, fourth, fifth and sixth signal controlledamplitude reducing means connected to said fourth amplitudediscriminator circuit, said fourth amplitude reducing means having afourth control signal terminal which, when energised, causes theeffective arnplitude of the input signal applied to said input terminalof said fourth amplitude discriminator circuit to be reduced by anamount representative of eight l digitrepresenting input signals, saidfifth amplitude reducing means having a fifth control signal terminal,which when energised, causes the effective amplitude of the input signalapplied to said input terminal of said fourth amplitude discriminatorcircuit to be reduced by an amount representative of four ldigit-representing input signals and said sixth amplitude reducing meanshaving a sixth control signal terminal which, when energised, causes theeffective amplitude of the inputsignal applied to said input terminal ofsaid fourth amplitude discriminator circuit to be reduced by an amountrepresentative of two l digit-representing input signals, said fourthamplitude discriminator circuit providing an output pulse at its outputterminal only when the resultant amplitude of the signal at its inputterminal after any reduction is at least equal to that representative ofone l digit-representing input signal, first, second and third delaydevice each having input and output terminals and each imposing a delaytime upon signals fed thereto equal to one digit interval time period ofsaid input pulse signal trains, circuitrneans for supplying the signaliii -output from the output terminal of said first' amplitudediscriminator `circuit to said first, second v.and :fourth i controlsignal terminals andto. said input terminal of said first delay device,circuit means for supplying the signal output from the output terminalof said second amplitude discriminator circuit to said third and fifthcontrol signal terminals and to said input terminal of said second delaydevice, circuit means for supplying the signal out put from the outputterminal of said third amplitude discriminator circuit to said sixthcontrol signal terminal and to said input terminal of said third delaydevice, circuit means for supplying the signal output from the outputterminal of said iirst delay devices to each of four different unusedinput terminals of said sum pulse deriving means, circuit means forapplying the signal output from the output terminal of said second delaydevice to two further unused input terminals of said sum pulse derivingmeans and circuit means for applying the signal output from the outputterminal of said third delay device to a further unused input terminalof said sum pulse deriving means, said output terminal of said fourthamplitude discriminator circuit providing an output pulse signal trainwhich is representative of the sum of the binary numbers represented bysaid simultaneously occurring input pulse signal trains.

17. An arrangement for effecting addition of binary numbers eachrepresented by .simultaneously occurring pulse signal trains whichcomprises a sum pulse deriving means having a plurality of separateinput terminals for connection one to each of the sour-ces ofsimultaneously occurring input signal trains and a single outputterminal at which is provided a signal pulse yvvhose amplitude isrepresentative of lthe analogue sum of the number of l digitrepresenting signals occurring simultaneously at said input terminals, afirst amplitude discriminator circuit hav ing an input terminal and anoutput terminal, circuit means supplying the signal output from theoutput terminal .of said sum pulse deriving means to said input terminalof said first amplitude discriminator circuit, said first amplitudediscriminator circuit providing an output signal pulse at said outputterminal only when the amplitude of the signal pulse applied to saidinput terminal thereof eX- ceeds the amplitude ,representative offifteen simultaneous l dig-it representing signals, a second amplitudediscriminator circuit having a first and second input terminals and anoutput terminal, circuit means for supplying the signal output from theoutput terminal of said sum pulse deriving means to said iir'st inputterminal of said second amplitude adding discriminat-or circuit, firstgate circuit means having a first control signal terminal and input andoutput terminals, said output terminal being connected to said secondinput terminal of said amplitude discrirninattor circuit, a lirst sourcelof subtraction signals representing sixteen l digit representingsignals, circuit means connectingy said input tenminal of said firstgate circuit means to said first subtraction signal source, said secondamplitude discrirninator circuit having a discrimination level wherebyit provides an output .signal pulse at its `output terminal only whenthe resultant amplitude of the input signal applied to its inputterminal less any subtraction signal applied to its second input`terminal exceeds the amplitude representing seven l digit representingsignals, a third amplitude discriminator circuit having a first, secondand third input terminals and an output terminal, circuit means forsupplying the signal output yfrom said output terminal of said pulse sumderiving means to said first input terminal of said third amplitudediscriminator, second gate circuit means having a second control signalterminal and input and output terminals, circuit means connecting saidoutput terminal of said second gate circuit means to the second inputterminal of said third amplitude discriminator circuit and forconnecting said input terminal of said gate means to said first sourceof subtraction signals, third gate cir-cuit means having a third controlsignal terminal and input and -output terminals, a

second .source of subtraction signalrepresenting eight l digitrepresenting signals, circuit means connecting said output terminal of.said third gate circuit means to said third input terminal of saidthird amplitude discriminator circuit and for connecting said inputterminal of said third gate 4circuit means to said second sourceofsubtraction signals, said third amplitude discriminator circuit having adiscrimination level whereby it provides an output signal pulse at itsoutput terminal only when the resultant amplitude of the input signal toits first input terminal less any subtraction signals .applied to itssecond and third input Iterminals exceeds the amplitude representingthree "1 digit representing signals, a fourth amplitude discriminatorcircuit having first, second, third and fourth input terminals .and anoutput terminal, circuit means for supplying the output signal from theoutput terminal of said sum pulse deriving means to said input terminalof said fourth `amplitude discriminator circuit, a fourth gate cir-`cuit means having a `fourth control signal terminal a-nd input andoutput terminals, means connecting said output terminal o-f said fourthgate circuit means to Isaid second input terminal `of said `fourthamplitude discriminator circuit and for connecting said input terminalof said fourth gate means to sai-d first source of subtraction signals,.a fifth gate circuit means having a fifth control signal terminal andinput and output terminals, means Iconnecting said output terminal ofsaid fifth gate circuit means to said third .input terminal of saidfourth amplitude discrimina tor cir-cuit and for connecting said inputterminal of said fifth gate circuit means to said second source ofsubtraction signals, a third source of subtraction signals representing-four l digit representing signals, a sixth gate circuit means having asixth control signal terminal and input and output terminals, meansconnecting said loutput terminal of said sixth gate circuit means tosaid fourth input terminal of said fourth amplitude discriminatorcircuit and for connecting said input terminal of said sixth gatecircuit means to said third source of subtraction signals, said fourthamplitude -discrirninator circuit having a discrimination level wherebyit provides an output signal pulse `at its output terminal only when theresultant amplitude of the input signal to its first input terminal lessany subtraction signals applied to its second, third and fourth inputterminals exceeds the amplitude representing one "1 digit representingsigna-l, a fifth amplitude discrirninator circuit having first, second,third, fourth .and fifth input terminals and an output terminal, circuitmeans for supplying the output signal from the output termi-nal of saidsum pulse deriving circuit to said first input terminal of said .fifthamplitude discriminator circuit7 a seventh Vgate circuit means having aseventh control signal terminal and input and output terminal, meansconnecting said output terminal of sai-d seventh gate circuit means tosaid second input terminal of said fifth amplitude discriminator circuitand for connecting said input terminal of said seventh gate circuitmeans to said first source of subtraction signals, an eighth gatecircuit means having an eighth control signal terminal and input andoutput terminals, means -connecting said output term ,of said eighthgate circuit means to said third input terminal of said fifth amplituded-iscriminator circuit and for connecting said input terminal of saideighth gate circuit mesas to said secon-d source of subtraction sign s,a ninth circuit means Shaving a ninth control signal terminal and inputand output terminals, Ameans con said output terminal of said ninth gatecircuit r to said fourth input terminal of said fifth a tudediscriminator circuit and for connecting said in terminal of said ninthgate circuit means to said third source of subtraction signals, a fourthsource of subtraction signals representing two l digit representing Fsignals, a tenth gate circuit having a tenth control signal terminal andinput and output terminals, means connecting sai-d output terminal ofsaid 'tenth gate circuit means to said fifth input terminal of saidfifth amplitude discriminator circuit and for connecting said inputterminal of said tenth gate circuit means to said fourth sourcesubtraction signals', said fifth amplitude `diiscrirninator circuithaving a discrimination level whereby `it provides an output pulse atits output terminal only when the resultant amplitude of the inputsignal to its first input terminal less .any subtraction signalssupplied to its second, third, ffourth, and fifth .input terminalsexceeds the amplitude representing zero, l digit representing signal,first, second, third and fourt-h delay devices each havi-ng input andoutput terminals and each imposing a delay time equal to appropriateintegral numbers of digit-intervals of said input pulse signal trains,circuit means connecting the output terminal of said first amplitudediscriminator circuit to said first, second, fourth and seventh controlsignal terminals gate circuits .and to the input terminal of said firstdelay device, circuit means connecting the output terminal of saidsecond amplitude discriminator circuit to said third, fifth and eighthcontrol signal terminals and to the input terminal of said second delaydevice, circuit means connecting the output terminal of said thirdamplitude discriminator circuit to said sixth and ninth control signalterminals and to said input terminal of said third delay .device randcircuit means connecting the output terminal of said fourth amplitudediscriminator circuit to said tenth control signal terminal and `to saidinput terminal of said fourth delay device and circuit means connectingthe output terminals of each of said first, second, third and fourthdelay devices to separate input terminals of said pulse amplitude addingmeans whereby said output terminal of said fifth amplitude discriminatorcircuit provides an electric pulse signal train representing in serialand dynamic f-orm lthe binary sum :of the numbers' .representedrespectively .by the pulse signal trains applied to said input terminalsof said sum pulse deriving means.

18. An arrangement accor-ding to claim 17 wherein said sum pulsederiving means comprises a thermionic valve arranged .in .ananode-follower type circuit, a plurality -of signal controlled switchingmeans one for each of .said input signal terminals, connection meansbetween said input terminals .and different related ones of saidswitching means for contro-lling such switching means by the pulsesignals of .said input pulse signal trains, said switching `means eachcontrolling the fiow of a predetermined value of bleed current in theinput circuit of said anode-follower type therrnionic valve circuit.

19. `An arrangement according to claim 18 wherein said switching meanseach comprise first and second diodes, the anode of said first diodebeing connected to the related input terminal and the anode of saidsecond diode being connected to the input circuit of said anode-followertype thermionic valve circuit `and the cathodes of said first and seconddiodes being interconnected and joined through a load resistance to asource of negative potential.

`20. An arrangement according to claim 17 wherein each of said amplitudediscriminator circuits comprise a thermionic valve arranged i-n an.anode-follower type circuit, a source lof bleed current for said anodeyfollower type c'icuit and signal controlled switching means connectedbetween .said source lof bleed current and said input of said anodefollower type circuit, said `switching .means having their operatingsignal supplied through said input terminals of said amplitudediscriminator circuit.

2l. An arrangement according to claim 17 wherein said sum pulse derivingmeans comprises a first thermionic valve and a second thermionic valve,circuit means coupling said anode of said first thermionic valve to saidcon- .triol grid :of said second thermionic valve, said coupling circuitmeans being traversable by direct current, a cathode load resistor forsaid second thermion-ic valve, circuit .means providing a feed-back pathtraversable by directcurrent between said cathode of said .secondthermionic valve .and the control grid of said first thermionic valve, aplurality of pairs of diodes each having interconnected cathodes, ionepair for each of said input terminals of said sum pulse deriving means,a source of negative potenacceso? tial, circuit means connecting theanode of one diode -of each pair to a separate one of said inputterminals, circuit means connecting the anodcs of the second diode ofeach of said pairs to the control grid of said rst thermionic valve anda plurality of common value `resistors each connected one between theinterconnected cathodes of each of said pairs of diodes and said sourceof negative potential.

22. An arrangement according to claim l7 wherein each of said amplitudediscriminator circuits comprises a first thcrmionic valve, a secondfthermionic valve, circuit means traversable by direct current betweensaid anode of said rst therinionic valve and the control grid of saidsecond therrnionic valve, a resistance network in the cathode circuit of.said second thermionic valve, said network cornprising lir'st, secondand third resistors' i-n series, means connected to the junction between`said rst and second resistances of said output terminal, a rstdiodehaving its cathode connected to the cathode of said second thermionicvalve `and its anode connected to the controlgrid of said rst thermionicvalve, a second diode having its anode connected to the junction betweensaid second and References Cited in the nie of this patent UNITED STATESPATENTS Swartzel June 11, 1946 Herbst Oct, 21, 1947 OTHER REFERENCESProgress Report (2) on the EDVAC, Moore School of E. E., Univ. of Pa., June 30, 1946, -declassified Feb. 13, 1947; pages 1-124, l-l-24A, 1-1-25,l-l-25A an B, 1-l-26, 1-1-26A, 1-127, and l-l-27A.

High Speed Computing Devi-ces, Engineering Research Associates, 1950,pages 285 to 289, inclusive,

